Specialized processor and reconfigurable architectures such as FPGAs and networks of dataflow-based micro-kernels are difficult to program. However, no programming model or language fully answers the needs of developers. Hence, they usually mix different programming models or use specific frameworks that try to provide the necessary functionalities, but do so at the expense of performance.
With POLCA, a first attempt will be made to jointly address the programmability challenges of embedded and high-performance computing infrastructures. POLCA aims to develop a mathematically-based approach, coupled with a toolchain that supports the right compilation, deployment, and execution configuration on the target architecture optimally exploiting its heterogeneous resources.
Project started in September 2013 with a first focus on the elaboration of the mathematical foundations and the requirements for the targeted use cases. CETIC will build up on the results and experience acquired from the PSOPP project, to develop relevant use cases that can benefit from FPGA based parallelization and acceleration. Signal processing and bioinformatics applications are primarily foreseen.
For CETIC, the development of POLCA approach is oriented toward improving the design process for complex and hybrid FPGA-based embedded systems. The benefits consist of a better design space exploration for those architectures, better management of the complexity and a quicker development cycle.