Jan Kuper, professor at the University of Twente in the Netherlands, co-founder of the spin-off QbayLogic in 2016 and partner of CETIC in the European project FP7 POLCA, will present CλaSH (pronounced: clash): a hardware design tool for FPGA based on the functional programming language Haskell.
Mainstream hardware design languages such as VHDL and Verilog have poor abstraction mechanisms and many attempts are done to design so-called High Level Synthesis languages. Most of these languages take an imperative perspective whereas CλaSH, on the other hand, starts from a functional perspective and is based on the functional language Haskell. That starting point offers high level abstraction mechanisms such as polymorphism, type derivation, higher order functions. Besides, it offers a direct simulation environment, every CλaSH specification is an executable program. During the presentation we will illustrate this with several examples such as elementary computational architectures, filters for signal processors, a simple processor.
People who are familiar with programming and interested in usage of other platforms than just a traditional processor. Some knowledge of hardware design is handy but not necessary.
Jan Kuper studied Logic and Mathematics and did his PhD under Henk Barendregt on the foundations of mathematics and computer science (1994). He worked in the areas of logic of language, theoretical computer science, and mathematical methods for architecture design. Currently he works at the Embedded Systems group of the University of Twente where he initiated the development of CλaSH. His lecturing experience comprises philosophical and mathematical logic, imperative and functional programming languages, and design of digital architectures. Together with Christiaan Baaij, he recently started the company QBayLogic to apply formal design methodologies to FPGA design.
CλaSH was partly developed during the European research project POLCA, in which CETIC and University of Twente are members of the consortium
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